In regard to a storage device using a NAND flash memory (which will be referred to as a NAND memory hereinafter) as a nonvolatile memory, for example, a solid-state drive (SSD) system, a demand for performance has recently become more rigorous. To enhance the performance while suppressing costs, developing a NAND controller that uses the NAND memory to a maximum extent will be more important in the future.
In the case of using the NAND memory that the number of rewritable (writable) times that varies depending on each chip or each block in a chip, to compress an amount of management information in a storage region, physical blocks may constitutes a block which is logical (which will be referred to as a logical block hereinafter) according to circumstances.
In this case, when physical block are randomly organized to constitute a logical block, a physical block having a considerably different number of rewritable times may be mixed in the logical block. In such a situation, since a defect occurs in dependent on a physical block having an extremely small number of rewritable times in the logical block, there is a problem that the defect occurs at an early point even though there is a physical block in which information can be still written as the NAND memory.